Design of a digital PLL with divide by 4/5 prescaler employing ring oscillator TDC and accumulator type DCO

Department of Electronics and Communication Ilahia College of Engineering and Technology Muvattupuzha, Ernakulam INDIA ______________________________________________________________________________________ Abstract: A digital PLL compares the circuit frequency with a reference frequency and adjusts the output using the feedback loop. A divide by 4/5 prescaler is used. The PLL locks when both the frequencies become equal. Analog PLLs are susceptible to noise and temperature variations. To deal with the problem of power dissipation and increased jitter, a digital PLL is prescribed. For reduced lock time and jitter, an accumulator type DCO and ring oscillator TDC is used. It attains fast lock time.